| 发明名称 |
CASCADED PLL FOR REDUCING LOW-FREQUENCY DRIFT IN HOLDOVER MODE |
| 摘要 |
A cascaded phase-locked loop (PLL) clock generation technique reduces frequency drift of a low-jitter clock signal in a holdover mode. An apparatus includes a first PLL circuit configured to generate a control signal based on a first clock signal and a first divider value. The apparatus includes a second PLL circuit configured to generate the first clock signal based on a low-jitter clock signal and a second divider value. The apparatus includes a third PLL circuit configured to generate the second divider value based on the first clock signal, a third divider value, and a second clock signal. The low-jitter clock signal may have a greater temperature dependence than the second clock signal and the second clock signal may have a higher jitter than the low-jitter clock signal. |
| 申请公布号 |
US2014225653(A1) |
申请公布日期 |
2014.08.14 |
| 申请号 |
US201313766035 |
申请日期 |
2013.02.13 |
| 申请人 |
SILICON LABORATORIES INC. |
发明人 |
Hara Susumu;Eldredge Adam B.;Batchelor Jeffrey S.;Gallant Daniel |
| 分类号 |
H03L7/23 |
主分类号 |
H03L7/23 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus comprising:
a first phase-locked loop (PLL) circuit configured to generate a control signal based on a first clock signal and a first divider value; a second PLL circuit configured to generate the first clock signal based on a low-jitter clock signal and a second divider value; and a third PLL circuit configured to generate the second divider value based on the first clock signal, a third divider value, and a second clock signal. |
| 地址 |
Austin TX US |
