| 摘要 |
<p>A semiconductor memory device (10) comprises: bit lines (BL,/BL) in pairs; a sense amplifier (400-0, 400-1) connected to each pair of the bit lines (BL,/BL); a word line (WL); a first memory cell (MC) that is connected to one bit line (BL) of each pair of the bit lines (BL,/BL) when the word line (WL) is activated; a second memory cell (/MC) that is connected to the other bit line (/BL) of each pair of the bit lines (BL, /BL) when the word line (WL) is activated; and a control circuit (81, 83, 86, 87) that activates the word line (WL) at a first potential during a first period, and then activates the word line (WL) at a second potential that is higher than the first potential during a second period that comes after the first period.</p> |
