发明名称 Dynamic partial power down of memory-side cache in a 2-level memory hierarchy
摘要 <p>A system and method are described for flushing a specified region of a memory side cache (MSC) within a multi-level memory hierarchy. For example, a computer system according to one embodiment comprises: a memory subsystem comprised of a non-volatile system memory and a volatile memory side cache (MSC) for caching portions of the non-volatile system memory; and a flush engine for flushing a specified region of the MSC to the non-volatile system memory in response to a deactivation condition associated with the specified region of the MSC.</p>
申请公布号 GB2510760(A) 申请公布日期 2014.08.13
申请号 GB20140008834 申请日期 2011.12.20
申请人 INTEL CORPORATION 发明人 RAJ K RAMANUJAN;GLENN HINTON;DAVID J ZIMMERMAN
分类号 G06F12/08 主分类号 G06F12/08
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