发明名称 |
Forward progress mechanism for stores in the presence of load contention in a system favoring loads by state alteration |
摘要 |
A multiprocessor data processing system includes a plurality of cache memories including a cache memory. The cache memory issues a read-type operation for a target cache line. While waiting for receipt of the target cache line, the cache memory monitors to detect a competing store-type operation for the target cache line. In response to receiving the target cache line, the cache memory installs the target cache line in the cache memory, and sets a coherency state of the target cache line installed in the cache memory based on whether the competing store-type operation is detected. |
申请公布号 |
US8806148(B2) |
申请公布日期 |
2014.08.12 |
申请号 |
US201213679351 |
申请日期 |
2012.11.16 |
申请人 |
International Business Machines Corporation |
发明人 |
Guthrie Guy L.;Le Hien M.;Shen Hugh;Stuecheli Jeff A.;Williams Derek E |
分类号 |
G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
Yudell Isidore Ng Russell PLLC |
代理人 |
Yudell Isidore Ng Russell PLLC ;Baca Matt |
主权项 |
1. A method in a multiprocessor data processing system including a plurality of cache memories including a cache memory, the method comprising:
in response to a read-type request of an associated processor core, issuing, by the cache memory, a read-type operation for a target cache line; while servicing the read-type request, monitoring, by the cache memory, to detect receipt of a competing store-type operation for the target cache line; in response to receiving the target cache line of the read-type operation:
installing the target cache line in a data array of the cache memory and, in a directory of the cache memory, setting a state field associated with the target cache line to a selected initial coherence state among multiple possible initial coherence states based on whether the competing store-type operation is detected while servicing the read-type request, wherein the setting includes:
selecting, as the initial coherence state, a first coherence state that designates the cache memory as a source of copies of the target cache line in response to not detecting a competing store-type operation while servicing the read-type request; andselecting, as the initial coherence state, a different second coherence state that does not designate the cache memory as a source of copies of the target cache line in response to detecting a competing store-type operation while servicing the read-type request. |
地址 |
Armonk NY US |