发明名称 Layout methods of integrated circuits having unit MOS devices
摘要 A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types.
申请公布号 US8803202(B2) 申请公布日期 2014.08.12
申请号 US201213558109 申请日期 2012.07.25
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Chuang Harry-Hak-Lay;Thei Kong-Beng;Hsu Jen-Bin;Cheng Chung Long;Liang Mong-Song
分类号 H01L27/118 主分类号 H01L27/118
代理机构 Slater and Matsil, L.L.P. 代理人 Slater and Matsil, L.L.P.
主权项 1. A semiconductor structure comprising: a first array; a second array substantially identical to the first array, wherein the first and the second arrays each comprise identical unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns, and wherein each of the unit MOS devices in the first and the second arrays comprises: an active region laid out in a first direction, wherein the first direction is selected from a row direction and a column direction; anda gate electrode laid out in a second direction perpendicular to the first direction, wherein the second direction is selected from the row direction and the column direction;a first plurality of contacts in the first array;a second plurality of contacts in the second array, wherein the first plurality of contacts and the second plurality of contacts have different layouts; a first unit MOS device in the first array; a second unit MOS device in the first array, wherein active regions of the first and the second unit MOS devices have different conductivity types; a third unit MOS device and a fourth unit MOS device in a same column of the first array and next to each other; a first contact electrically connecting sources of the third and the fourth unit MOS devices; and a second contact electrically connecting drains of the third and the fourth unit MOS devices, wherein gates of the third and the fourth unit MOS devices are electrically connected.
地址 Hsin-Chu TW