Semiconductor memory device for controlling write recovery time

摘要

A semiconductor memory device includes a CAS latency mode detecting means for outputting a CAS latency control signal in response to a CAS latency mode; and an auto-precharge control means for controlling timing of an auto-precharge operation in response to the CAS latency control signal.

主权项

1. A method of controlling timing of a precharge operation according to a CAS latency mode, the method comprising:
detecting the CAS latency mode; outputting a delay signal corresponding to the CAS latency mode; outputting a delayed auto-precharge signal after delaying an auto-precharge signal by passing the auto-precharge signal through one or more unit delays; and performing an auto-precharge operation synchronized to a clock signal in response to the delayed auto-precharge signal, wherein the number of the unit delays where the auto-precharge signal passes through is determined by the delay signal.