| 主权项 |
1. A network processing device packet buffering subsystem comprising:
a first-in first out (FIFO) memory comprising a plurality of FIFO buffers, each associated with a source index, to receive multiplexed packet data marked with source indices and sort the multiplexed packet data to the FIFO buffers according to source index; a plurality of counters, associated respectively with the plurality of FIFO buffers, to track a size of each packet as it is received into each FIFO buffer from the multiplexed packet data; and segmentation logic to output from the FIFO memory a segment of a packet being received into a given one of the FIFO buffers when the packet data accumulated in that given FIFO buffer for the received packet exceeds a selected data length, the selected data length being less than an amount of data than can be transmitted through a switch fabric associated with the buffering subsystem during a single epoch of time; wherein the segmentation logic allows the packet data accumulated for a given segment to exceed the selected data length by up to a selected overflow amount when lengthening the given segment will allow the given segment to be a last segment for its corresponding packet; wherein the segmentation logic delays outputting the given segment until it determines whether the given segment can be made the last segment by extending the given segment up to the selected overflow amount. |
