Memoryless sliding window histogram based BIST

摘要

A chip with a built-in self-test (BIST) component capable of testing the linearity of an ADC is described herein. The BIST component uses hardware registers to facilitate a sliding histogram technique to save space on the chip. A subset of detected digital codes are analyzed, and DNL and INL calculations are performed by a controller to determine whether any of the digital codes in the subset exceed maximum or minimum DNL and INL thresholds. New digital codes being detected by the ADC are added to the subset as lower-value digital codes are pushed out of the subset, maintaining the same number of digital codes being analyzed as the subset moves from lower codes detected during lower voltages to higher codes detected at higher voltages. A synchronizer and pointer ensure that the subset moves through the digital codes at the same rate as the analog input ramp source.

主权项

1. A system for determining nonlinearity characteristics of an analog-to-digital converter (ADC), comprising:
a built-in self-test (BIST) configured to determine differential nonlinearity (DNL) values for each digital code in a subset of digital codes generated by the ADC in response to an input analog voltage; a window synchronizer configured to add at least one digital code to the subset; and a controller configured to make a determination about the ADC based on one or more counters indicating a quantity of the DNL values exceeding at least one threshold DNL value.