Chip package

摘要

A chip package includes: a substrate having a first surface, a second surface, and a side surface connecting the first and the second surfaces; a dielectric layer located on the first surface; conducting pads comprising a first and a second conducting pads located in the dielectric layer; openings extending from the second surface towards the first surface and correspondingly exposing the conducting pads, wherein a first opening of the openings and a second opening of the openings next to the first opening respectively expose the first and the second conducting pads and extend along a direction intersecting the side surface of the substrate to respectively extend beyond the first and the second conducting pads; and a first and a second wire layers located on the second surface and extending into the first the second openings to electrically contact with the first and the second conducting pads, respectively.

主权项

1. A chip package, comprising:
a substrate having a first surface, an opposite second surface, and a side surface connecting the first surface and the second surface; a dielectric layer located on the first surface of the substrate; a plurality of conducting pads at least comprising a first conducting pad and a second conducting pad located in the dielectric layer; a plurality of openings extending from the second surface towards the first surface of the substrate and respectively and correspondingly exposing the conducting pads, wherein at least a first opening of the openings and at least a second opening of the openings adjacent to the first opening respectively expose the first conducting pad and the second conducting pad and extend towards the side surface of the substrate to extend beyond the first conducting pad and the second conducting pad in a direction of a normal vector of the side surface; a first wire layer and a second wire layer located on the second surface of the substrate and extend into the first opening and the second opening to electrically connect to the first conducting pad and the second conducting pad, respectively; and a seal ring structure disposed in the dielectric layer, wherein the seal ring structure comprises a plurality of separate seal rings respectively disposed along a periphery of the substrate and located outside of projection regions of the first opening and the second opening on the dielectric layer.