Semiconductor package

摘要

A semiconductor package may include a substrate, a semiconductor chip disposed on the substrate, a communication terminal and a static electricity inducing terminal connected to a ground. The package may include a first sealant that comprises a voltage sensitive material and that covers the semiconductor chip and a static electricity blocking layer that provides a conductive pathway from the first sealant to only the static electric inducing terminal. The static electricity blocking layer may prevent the communication terminal from being electrically connected to the first sealant. If a buildup of charge is applied to the device, the first sealant may become polarized and/or conductive. The extra voltage may travel through the first sealant to the static electricity inducing terminal via an opening in the static electricity blocking layer. The semiconductor chip and the communication terminal may not be affected by the extra charge.

主权项

1. A semiconductor package comprising:
a substrate; at least a first semiconductor chip disposed on the substrate; at least a first communication terminal disposed on the substrate, the first communication terminal being electrically connected to the first semiconductor chip and to an external source; at least a first inducing terminal disposed on the substrate, the first inducing terminal being electrically connected to the semiconductor chip and to a ground; an external covering enclosing at least a portion of the first semiconductor chip, an external surface of the external covering being exposed to the outside of the semiconductor package; a static electricity blocking layer disposed between the external covering and the first inducing terminal and between the external covering and the first communication terminal, the static electricity blocking layer configured to prevent a conductive pathway from being formed between the external covering and the first communication terminal; and at least a first opening formed in the static electricity blocking layer, wherein the external covering is configured to be electrically connected to the first inducing terminal via the first opening.