Integrated circuit including semiconductor memory devices having stack structure

摘要

An integrated circuit includes a plurality of mode register set (MRS) setting blocks configured to generate a plurality of additive latency (AL) codes in response to an MRS signal, and a decoding unit configured to decoding the plurality of AL codes in response to a stack information signal to generate a plurality of AL setting signals.

主权项

1. An integrated circuit comprising:
a plurality of mode register set (MRS) setting blocks configured to generate a plurality of additive latency (AL) codes in response to an MRS signal; a decoding unit configured to decoding the plurality of AL codes in response to a stack information signal to generate a plurality of AL setting signals; and a decoding operation control unit configured to control an operation of the decoding unit to activate a reserved signal or a AL-complementary setting signal in response to a stack information signal when the plurality of AL codes have a given value, wherein the stack information signal is activated when the integrated circuit includes a plurality of stacked semiconductor memory devices, and wherein the decoding operation control unit controls the decoding unit to activate the reserved signal in response to the plurality of AL codes of the given value in a case where the stack information signal is deactivated.