发明名称 |
Semiconductor memory device |
摘要 |
According to one embodiment, there is provided a semiconductor memory device including a memory cell. The memory cell includes a first driving transistor, a first load transistor, a first read transfer transistor, a first write transfer transistor, a second driving transistor, a second load transistor, a second read transfer transistor, a second write transfer transistor, and one or more variable resistance elements. The one or more variable resistance elements has resistance that changes depending on a direction of a bias applied to both terminals. The one or more variable resistance elements are arranged in at least one of a portion between a first storage node and a first write transfer transistor and a portion between a second storage node and a second write transfer transistor. |
申请公布号 |
US8804403(B2) |
申请公布日期 |
2014.08.12 |
申请号 |
US201313969221 |
申请日期 |
2013.08.16 |
申请人 |
Kabushiki Kaisha Toshiba |
发明人 |
Kushida Keiichi |
分类号 |
G11C14/00 |
主分类号 |
G11C14/00 |
代理机构 |
Knobbe, Martens, Olson & Bear, LLP |
代理人 |
Knobbe, Martens, Olson & Bear, LLP |
主权项 |
1. A semiconductor memory device comprising a memory cell including:
a first driving transistor connected to a first storage node; a first load transistor connected to the first storage node; a first read transfer transistor connected between the first storage node and a first read bit line; a first variable resistance element which has one terminal connected to the first storage node and has another terminal, a resistance of which changes depending on a voltage applied to both terminals; a first write transfer transistor arranged between a first write bit line and the first variable resistance element; a second driving transistor connected to a second storage node; a second load transistor connected to the second storage node; a second read transfer transistor arranged between the second storage node and a second read bit line; a second write transfer transistor arranged between the second storage node and a second write bit line, wherein a source of the first driving transistor and a source of the second driving transistor are connected to a first supply voltage and data written to the first storage node is saved to the first variable resistance element in response to the first supply voltage changing between a plurality of different voltage levels. |
地址 |
Tokyo JP |