发明名称 Three-dimensional multilayer solenoid transformer
摘要 This disclosure provides implementations of inductors, transformers, and related processes. In one aspect, a device includes a substrate having first and second surfaces. A first inducting arrangement includes a first set of vias, a second set of vias, a first set of traces arranged over the first surface connecting the first and second vias, and a second set of traces arranged over the second surface connecting the first and second vias. A second inducting arrangement is inductively-coupled and interleaved with the first inducting arrangement and includes a third set of vias, a fourth set of vias, a third set of traces arranged over the first surface connecting the third and fourth vias, and a fourth set of traces arranged over the second surface connecting the third and fourth vias. One or more sets of dielectric layers insulate portions of the traces from one another.
申请公布号 US8803648(B2) 申请公布日期 2014.08.12
申请号 US201213463257 申请日期 2012.05.03
申请人 QUALCOMM MEMS Technologies, Inc. 发明人 Lo Chi Shun;Kim Jonghae;Zuo Chengjie;Yun Changhan Hobie
分类号 H01F5/00;H01F27/28;H01F27/29 主分类号 H01F5/00
代理机构 Weaver Austin Villeneuve & Sampson, LLP 代理人 Weaver Austin Villeneuve & Sampson, LLP
主权项 1. A device comprising: a substrate having a first surface and a second surface opposite the first surface; a first inducting arrangement including a plurality of first conductive pathways that together form a first conductive path, the first conductive path having a first axis of revolution, the plurality of first conductive pathways including a first set of vias extending at least from the first surface to the second surface through the substrate, a second set of vias extending at least from the first surface to the second surface through the substrate, a first set of traces arranged over the first surface that connect the first set of vias with the second set of vias, and a second set of traces arranged over the second surface that connect the first set of vias with the second set of vias; a second inducting arrangement inductively-coupled with and interleaved with the first inducting arrangement and including a plurality of second conductive pathways that together form a second conductive path, the second conductive path having a second axis of revolution, the first axis of revolution being laterally offset from and parallel to the second axis of revolution, at least part of the first axis of revolution being inside the second inducting arrangement, the second axis of revolution being inside the first inducting arrangement, the plurality of second conductive pathways including a third set of vias extending at least from the first surface to the second surface through the substrate, a fourth set of vias extending at least from the first surface to the second surface through the substrate, a third set of traces arranged over the first surface that connect the third set of vias with the fourth set of vias, and a fourth set of traces arranged over the second surface that connect the third set of vias with the fourth set of vias; a first set of one or more dielectric layers that insulate portions of the first set of traces from portions of the third set of traces; and a second set of one or more dielectric layers that insulate portions of the second set of traces from portions of the fourth set of traces; wherein: the first set of traces are formed from a first conductive layer deposited and patterned on the first surface; the one or more dielectric layers that insulate portions of the first traces from portions of the third traces include a first dielectric layer deposited and patterned over the first surface so as to cover portions of the first set of traces; the third set of traces are formed from a third conductive layer deposited and patterned over the first dielectric layer; the fourth set of traces are formed from a fourth conductive layer deposited and patterned on the second surface; the one or more dielectric layers that insulate portions of the second traces from portions of the fourth traces include a second dielectric layer deposited and patterned over the second surface so as to cover portions of the fourth set of traces; and the second set of traces are formed from a second conductive layer deposited and patterned over the second dielectric layer.
地址 San Diego CA US