发明名称 Wireless communication receiver, a wireless communication receiving method and a television receiver
摘要 The present invention relates to a wireless communication receiver, wireless communication receiving method and television receiver. The wireless communication receiver has signal processing circuits including a first signal processing circuit and a second signal processing circuit, a data storage module, and a deinterleaver. The first signal processing circuit receives a wireless communication signal and then performs a first signal processing to generate a first output data according to the wireless communication signal. The deinterleaver stores the first output data into the data storage module, and retrieves a deinterleaved data corresponding to the first output signal from the data storage module. The second signal processing circuit performs a second signal processing to generate a second output data according to the deinterleaved data. The data storage module is shared by the deinterleaver and at least one of the signal processing circuits for data storage, thereby effectively reducing the production cost.
申请公布号 US8804049(B2) 申请公布日期 2014.08.12
申请号 US200812865398 申请日期 2008.01.31
申请人 Mediatek Inc. 发明人 Yang Shun-An
分类号 H04N5/44;H04N5/455 主分类号 H04N5/44
代理机构 代理人 Hsu Winston;Margo Scott
主权项 1. A wireless communication receiver, comprising: a data storage module; a deinterleaver, coupled to the data storage module, for storing a first output data into the data storage module, and retrieving a deinterleaved data corresponding to the first output data from the data storage module; and a plurality of signal processing circuits, comprising: a first signal processing circuit, coupled to the deinterleaver, for receiving a wireless communication signal, and generating the first output data by performing a first signal processing operation according to the wireless communication signal, wherein the first signal processing circuit comprises: a signal receiving circuit for receiving the wireless communication signal and accordingly generating a received signal;a channel estimation/equalization circuit for generating a channel estimation/equalization output by performing a channel estimation/equalization according to the received signal; anda channel state information generation circuit for generating a channel state information, wherein the first output data includes the channel estimation/equalization output and the channel state information; anda second signal processing circuit, coupled to the deinterleaver, for generating a second output data by performing a second signal processing operation according to the deinterleaved data; wherein the data storage module is shared by the deinterleaver and the second signal processing circuit for data storage, and the deinterleaver is further coupled to the channel estimation/equalization circuit and the channel state information generation circuit, and utilized for storing the channel estimation/equalization output and the channel state information into the data storage module, respectively, and retrieving a deinterleaved data corresponding to the channel estimation/equalization output and a deinterleaved data corresponding to the channel state information from the data storage module, respectively.
地址 Science-Based Industrial Park, Hsin-Chu TW