发明名称 Cholesky decomposition in an integrated circuit device
摘要 Efficient and scalable circuitry for performing Cholesky decomposition is based on two types of processing elements. A first type of processing element provides inverse square root and multiplication operations. A second type of processing element includes a first computation path for outputting an inner product difference element and a second computation path for outputting an inner product element. Processing elements of the first and second type may be cascaded to achieve a decomposition of a matrix of an arbitrary size. The circuitry is flexible to allow different throughput requirements, and can be optimized to reduce latency and resource consumption.
申请公布号 US8805911(B1) 申请公布日期 2014.08.12
申请号 US201113149661 申请日期 2011.05.31
申请人 Altera Corporation 发明人 Xu Lei;Langhammer Martin
分类号 G06F7/38 主分类号 G06F7/38
代理机构 Ropes & Gray LLP 代理人 Ropes & Gray LLP ;Ingerman Jeffrey H.
主权项 1. Circuitry for decomposing an input matrix, the circuitry comprising: a plurality of processing elements of a first type for outputting respective elements of a triangulated resultant matrix; and a plurality of processing elements of a second type respectively coupled to outputs of the plurality of processing elements of the first type, for outputting respective inner product elements corresponding to respective elements of said resultant matrix, wherein each of the inner product elements is a single number.
地址 San Jose CA US