Delay locked loop (DLL) system for a memory device with wide operating frequency via a variable supply applied to a delay line

摘要

A DLL system in a memory device with wide frequency application includes: a clock receiver that generates a clock for the DLL system; a delay line, coupled to the clock receiver, for receiving the generated clock and delaying the clock according to a received power supply; a power regulator, for generating the power supply to the DLL delay line according to a bias; a control logic, coupled to the clock receiver, for generating a plurality of logic signals respectively corresponding to a plurality of frequency ranges of the clock; and a bias generator, coupled between the control logic and the power regulator, for providing the bias to the power regulator, wherein the value of the bias is according to a logic signal output by the control logic.

主权项

1. A delay locked loop (DLL) system in a memory device with wide frequency application, comprising:
a clock receiver that generates a clock for the DLL system; a delay line, coupled to the clock receiver, for receiving the generated clock and delaying the clock according to a received power supply; a power regulator, for generating a power supply to the delay line according to a bias; a control logic, coupled to the clock receiver, for generating a plurality of logic signals respectively corresponding to a plurality of frequency ranges of the clock; and a bias generator, coupled between the control logic and the power regulator, for providing the bias to the power regulator, wherein the value of the bias is according to a logic signal output by the control logic.