Method and system for layout parasitic estimation

摘要

A system comprises an electronic design automation (EDA) tool, for generating a schematic design of an integrated circuit (IC), generating a layout from the schematic design, editing the layout, and verifying the schematic design and layout. At least one non-transitory, computer readable storage medium, is provided for storing data representing the schematic design and the layout, the layout having a network of routing paths connecting at least two active layer devices of the IC design. An RC tool is provided for computing estimated parasitic capacitances of the routing paths of the network before verifying the schematic design and layout, and for inserting a capacitor corresponding to the estimated parasitic capacitance into the data representing the schematic design of the IC. A first device level simulation tool for simulating performance of the network based on the at least two active layer devices and the estimated parasitic capacitances.

主权项

1. A method comprising:
(a) generating a layout of an integrated circuit (IC) design using an electronic design automation (EDA) tool, the layout having a network of routing paths connecting at least two active layer devices of the IC design; (b) computing estimated parasitic capacitances of the routing paths of the network; (c) performing a first device level simulation of the network based on the at least two active layer devices and the estimated parasitic capacitances; (d) using the EDA tool to revise the layout or a device of the IC design if a result of the first device level simulation fails to satisfy an IC specification;
wherein steps (b), (c) and (d) are performed one or more times before performing design rule checks and before performing layout-versus-schematic checks, until a result of the first device level simulation satisfies the IC specification; and (e) outputting the revised layout of the IC design to a non-transitory, machine readable storage medium after completion of steps (b) to (d), to be accessed by the EDA tool to perform design verification.