Vertical transistor having reduced parasitic capacitance

摘要

A transistor includes a substrate and an electrically conductive material layer stack positioned on the substrate. The electrically conductive material layer stack includes a reentrant profile. A first electrically insulating material layer positioned is in contact with a first portion of the electrically conductive material layer stack. A second electrically insulating material layer is conformally positioned in contact with the first electrically insulating layer, and conformally positioned in contact with a second portion of the electrically conductive material layer stack, and conformally positioned in contact with at least a portion of the substrate.

主权项

1. A transistor comprising:
a substrate; an electrically conductive material layer stack positioned on the substrate, the electrically conductive material layer stack including a reentrant profile; a first electrically insulating material layer positioned in contact with a first portion of the electrically conductive material layer stack on a surface of the first electrically conductive material layer stack opposite the substrate; a second electrically insulating material layer conformally positioned in contact with the first electrically insulating layer, and conformally positioned in contact with a second portion of the electrically conductive material layer stack, and conformally positioned in contact with at least a portion of the substrate; a semiconductor material layer conformally positioned in contact with the second electrically insulating layer; and a first electrode and a second electrode in contact with distinct portions of the semiconductor material layer, the first electrode located on the electrically conductive material layer stack, the second electrode not located on the electrically conductive material layer stack, the first electrically insulating material layer separating the first electrode from the electrically conductive material layer stack.