Reconfigurable sequencer structure

摘要

A cell element field for data processing, having function cell means for execution of algebraic and/or logic functions and memory cell means for receiving, storing and/or outputting information is described. Function cell-memory cell combinations are formed in which a control connection leads from the function cell means to the memory cell means.

主权项

1. A data processor chip comprising:
a plurality of data processing elements each including at least one arithmetic-logic-unit; a plurality of memory elements adapted for storing at least one of program data and program code; at least one input/output element adapted for transmitting data to and receiving data from at least one of a high level memory and peripherals; and a bus system; wherein:
each of the data processing, memory, and input/output elements is dedicated to its respective function and separate from each other;the bus system interconnects the data processing, memory, and input/output elements for transmitting data between specific ones of the elements according to a setting of the bus system at runtime; andeach of the data processing, memory, and input/output elements is flexibly connectable for transmitting data to at least one other of the data processing, memory, and input/output elements depending on the setting of the bus system at runtime.