发明名称 |
Electrostatic discharge (ESD) device and method of fabricating |
摘要 |
A structure and method of fabricating electrostatic discharge (EDS) circuitry in an integrated circuit chip by integrating a lateral bipolar, either a p-n-p with a NMOSFET or a n-p-n with a PMOSFET within a triple well. The lateral bipolar preferably includes diodes at the I/O and/or the VDDs of the circuitry. |
申请公布号 |
US8803276(B2) |
申请公布日期 |
2014.08.12 |
申请号 |
US201314073119 |
申请日期 |
2013.11.06 |
申请人 |
International Business Machines Corporation |
发明人 |
Chang Shunhua;Chatty Kiran V.;Gauthier Robert J.;Muhammad Mujahid |
分类号 |
H01L23/58 |
主分类号 |
H01L23/58 |
代理机构 |
Roberts Mlotkowski Safran & Cole, P.C. |
代理人 |
Le Strange Michael;Roberts Mlotkowski Safran & Cole, P.C. |
主权项 |
1. In a structure of an integrated circuit chip, the structure comprising:
a substrate with a region of triple wells, N-Wells separated by and isolated from a P-Well therein; a MOSFET with a source, drain and gate in the isolated P-Well; a lateral p-n-p having a base, emitter and collector in each of the N-Wells and integrated with the MOSFET; an input/output pad coupled to the emitters of the lateral p-n-p and to the drain of the MOSFET; and VDD applied to each of the bases of the lateral p-n-p, the source and the gate of the MOSFET and the collectors of the lateral p-n-p and source of the MOSFET being connected to ground, whereby a parasitic lateral n-p-n turns on and safely discharges ESD current to ground when an ESD event occurs by creating an avalanche generation of carriers near the drain of the P-Well junction and an increase in the lateral p-n-p collector current. |
地址 |
Armonk NY US |