Vertical mirror in a silicon photonic circuit

摘要

A vertical total internal reflection (TIR) mirror and fabrication thereof is made by creating a re-entrant profile using crystallographic silicon etching. Starting with an SOI wafer, a deep silicon etch is used to expose the buried oxide layer, which is then wet-etched (in HF), opening the bottom surface of the Si device layer. This bottom silicon surface is then exposed so that in a crystallographic etch, the resulting shape is a re-entrant trapezoid with facets These facets can be used in conjunction with planar silicon waveguides to reflect the light upwards based on the TIR principle. Alternately, light can be coupled into the silicon waveguides from above the wafer for such purposes as wafer level testing.

主权项

1. A vertical mirror on a silicon photonic circuit, comprising:
a silicon device wafer; a buried oxide (BOX) layer under the silicon device wafer; a handle wafer doped with a p-type dopant under the BOX layer; and a trapezoid shaped area having a bottom side defined by the handle wafer, opposite vertical sides defined by the BOX layer, and inwardly angled facets above the vertical sides defined by the silicon device wafer, wherein the facets act as vertical total internal reflection (TIR) mirrors.