Nanowire transistor with surrounding gate

摘要

One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.

主权项

1. An array of transistors comprising:
a crystalline substrate; a plurality of transistors in rows and columns on the crystalline substrate, wherein row spacing between adjacent rows and column spacing between adjacent columns is determined by a minimum feature size (F) for a lithographic process; and each transistor in the transistor array comprises:
a first source/drain region in the crystalline substrate;a semiconductor pillar on the crystalline substrate in contact with the first source/drain region, the semiconductor pillar having a cross-sectional dimension in a direction substantially parallel with a surface of the substrate that is less than the minimum feature size F;a second source/drain region in a top portion of the semiconductor pillar;a gate insulator around the semiconductor pillar; anda surrounding gate around and separated from the semiconductor pillar by the gate insulator.