Reliability, availability, and serviceability in a memory device

摘要

Embodiments of the invention are generally directed to improving the reliability, availability, and serviceability of a memory device. In some embodiments, a memory device includes a memory core having a first portion to store data bits and a second portion to store error correction code (ECC) bits corresponding to the data bits. The memory device may also include error correction logic on the same die as the memory core. In some embodiments, the error correction logic enables the memory device to compute ECC bits and to compare the stored ECC bits with the computed ECC bits.

主权项

1. A memory device comprising:
a memory core having a first portion to store data bits and a second portion to store error correction code (ECC) bits (stored ECC bits) corresponding to the data bits, the memory core comprising at least one split bank pair that has the first portion in a first memory bank and the second portion a second memory bank, wherein, in error check mode, data bits are stored in the first memory bank and corresponding error check bits are stored in the second memory bank, the memory core to support either error check mode or non-error check mode in response to a register bit; and error correction logic on the same die as the memory core, the error correction logic including ECC computation logic to compute ECC bits (computed ECC bits) corresponding to the data bits.