发明名称 Methods for designing integrated circuits employing voltage scaling and integrated circuits designed thereby
摘要 Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to implement a layout from the functional IC design that meets the performance objectives and (6) performing a timing signoff of the layout at the optimization target voltage.
申请公布号 US8806408(B2) 申请公布日期 2014.08.12
申请号 US200912364918 申请日期 2009.02.03
申请人 Agere Systems Inc. 发明人 Parker James C.;Rao Vishwas M.;Schneider, Jr. Clayton E.;Sheets Gregory W.;Subbarao Prasad
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项 1. A method of designing an integrated circuit, comprising: generating a functional design for said integrated circuit; determining performance objectives for said integrated circuit; determining an optimization target voltage for said integrated circuit; determining whether said integrated circuit needs voltage scaling to achieve said performance objectives at said optimization target voltage and, if so, selecting between employing static voltage scaling or adaptive voltage scaling; using said optimization target voltage to synthesize a netlist from said functional integrated circuit design that meets said performance objectives, wherein said using is performed by a processor determining a routing at said optimization target voltage; implementing a layouy of said integrated circuit from said netlist; and performing a timing signoff of said layout at said optimization target voltage.
地址 Wilmington DE US