发明名称 |
Current mode logic circuit and method |
摘要 |
A circuit includes a bias generating circuit, an operational amplifier, and a current mode logic circuit. The operational amplifier has a first input terminal, a second input terminal, and an output terminal. The bias generating circuit is configured to provide a first bias voltage to the first terminal. The second terminal is configured to receive a second bias voltage. The second terminal and the output terminal are configured to form a negative feedback loop. The output terminal is coupled with the current mode logic circuit. |
申请公布号 |
US8803611(B2) |
申请公布日期 |
2014.08.12 |
申请号 |
US201213588830 |
申请日期 |
2012.08.17 |
申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Chen Wei Chih |
分类号 |
H03F3/45 |
主分类号 |
H03F3/45 |
代理机构 |
Slater and Matsil, L.L.P. |
代理人 |
Slater and Matsil, L.L.P. |
主权项 |
1. A circuit comprising:
a bias generating circuit; an operational amplifier having a first input terminal, a second input terminal, and an output terminal; a first resistive device and a second resistive device, wherein a first end of each first resistive device and second resistive device is configured to receive a supply voltage, resulting in a first current flowing through the first resistive device and the first input terminal and a second current flowing through the second resistive device and the second input terminal; and a current mode logic circuit, wherein
the bias generating circuit is configured to provide a first bias voltage to the first terminal;the second input terminal is configured to receive a second bias voltage;the second input terminal and the output terminal are configured to form a negative feedback loop; andthe output terminal is coupled with the current mode logic circuit. |
地址 |
Hsin-Chu TW |