Dynamic high speed buffer with wide input noise margin

摘要

This disclosure provides examples of circuits, devices, systems, and methods for providing high speed operation and a high noise margin. In one implementation, a circuit includes a first buffer configured to receive an incoming signal and a control signal and to generate an output signal based on the incoming signal. The first buffer exhibits a first hysteresis range while configured in a first hysteresis state and a second hysteresis range while configured in a second hysteresis state. The first buffer is configured to transition from the first to the second hysteresis state and vice versa in response to the control signal. The circuit includes a second buffer configured to receive the incoming signal and to generate the control signal based on the incoming signal. The second buffer exhibits a third hysteresis range with a lower threshold and an upper threshold.

主权项

1. A circuit comprising:
a first buffer configured to receive an incoming signal and a control signal and to generate an output signal based on the incoming signal, the first buffer exhibiting a first hysteresis range while configured in a first hysteresis state, the first buffer exhibiting a second hysteresis range while configured in a second hysteresis state, the first buffer being configured to transition from the first hysteresis state to the second hysteresis state and vice versa in response to the control signal; and a second buffer configured to receive the incoming signal and to generate the control signal based on the incoming signal, the second buffer exhibiting a third hysteresis range with a lower threshold more negative than at least a lower threshold of the second hysteresis range, and an upper threshold more positive than at least an upper threshold of the first hysteresis range.