Graphene and nanotube/nanowire transistor with a self-aligned gate structure on transparent substrates and method of making same

摘要

Transistor devices having a self-aligned gate structure on transparent substrates and techniques for fabrication thereof are provided. In one aspect, a method of fabricating a transistor device includes the following steps. A channel material is formed on a transparent substrate. Source and drain electrodes are formed in contact with the channel material. A dielectric layer is deposited on the channel material. A photoresist is deposited on the dielectric layer and developed using UV light exposure through the transparent substrate. A gate metal(s) is deposited on the exposed portions of the dielectric layer and the undeveloped portions of the photoresist. The undeveloped portions of the photoresist are removed along with portions of the gate metal over the source and drain regions to form a gate of the device on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes.

主权项

1. A method of fabricating a transistor device, comprising the steps of:
providing a transparent substrate; forming a channel material on the substrate; forming source and drain electrodes over, and in direct contact with, both the channel material and the transparent substrate, such that the source and drain electrodes cover opposite ends of the channel material and contact a surface of the transparent substrate beneath the channel material; depositing a dielectric layer on, and in direct contact with, each of the channel material, the source and drain electrodes, and the transparent substrate, wherein the dielectric layer is deposited to a thickness that permits UV light to pass therethrough; depositing a photoresist on the dielectric layer; developing the photoresist using UV light exposure through the transparent substrate, wherein exposure of portions of the photoresist is blocked by the source and drain electrodes; removing developed portions of the photoresist exposing portions of the dielectric layer, wherein undeveloped portions of the photoresist remain over the source and drain electrodes; depositing at least one gate metal on the exposed portions of the dielectric layer and the undeveloped portions of the photoresist; and removing the undeveloped portions of the photoresist along with portions of the gate metal over the source and drain regions, wherein a remaining portion of the gate metal between the source and drain region electrodes forms a gate of the device on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes, and wherein following removal of the undeveloped portions of the photoresist along with the portions of the gate metal over the source and drain regions only the dielectric layer remains present on, and in direct contact with, a top surface of each of the source and drain electrodes.