Time division multiplexed multiport memory implemented using single-port memory elements

摘要

Integrated circuits having single-port memory elements may be provided. The single-port memory elements may be controlled using a control circuit to emulate multiport functionality. In one suitable embodiment, the control circuit may be an arbitration circuit configured to execute a memory request as soon as it is received by the arbitration circuit. Requests received while a current memory access is being performed may be put on hold until the current memory access has been completed. In another suitable embodiment, the control circuit may be a sequencing circuit configured to service memory access requests from a synchronous port and an asynchronous port. Memory access requests received at the synchronous port may be serviced immediately, whereas memory access requests received at the asynchronous port may be synchronized to an internal memory clock signal and may be serviced after a preceding memory access request associated with the synchronous port has been serviced.

主权项

1. A method for operating a dual-port memory having first and second ports, wherein the dual-port memory includes an array of single-port memory elements, the method comprising:
receiving a first memory access request and an associated first clock signal at the first port; receiving a second memory access request and an associated second clock signal at the second port; in response to detecting a rising clock edge in the second clock signal with a control circuit, generating a third clock signal and servicing the second memory access request; and while the second memory access request is being serviced, sampling the first memory access request using the third clock signal.