发明名称 Cache replacement using active cache line counters
摘要 An apparatus for performing data caching comprises at least one cache memory including multiple cache lines arranged into multiple segments, each segment having a subset of the cache lines associated therewith. The apparatus further includes a first plurality of counters, each of the counters being operative to track a number of active cache lines associated with a corresponding one of the segments. At least one controller included in the apparatus is operative to receive information relating to the number of active cache lines associated with a corresponding segment from the first plurality of counters and to implement a cache segment replacement policy for determining which of the segments to replace as a function of at least the information relating to the number of active cache lines associated with a corresponding segment.
申请公布号 US8806137(B2) 申请公布日期 2014.08.12
申请号 US201113163198 申请日期 2011.06.17
申请人 LSI Corporation 发明人 Rabinovitch Alexander;Dubrovin Leonid
分类号 G06F12/12 主分类号 G06F12/12
代理机构 Otterstedt, Ellenbogen & Kammer, LLP 代理人 Otterstedt, Ellenbogen & Kammer, LLP
主权项 1. An apparatus for performing data caching, comprising: at least one cache memory including a plurality of cache lines arranged into a plurality of segments, each segment having a subset of the cache lines associated therewith; a first plurality of counters, each of the first plurality of counters being operative to track a number of active cache lines associated with a corresponding one of the segments; and at least one controller operative to receive information relating to the number of active cache lines associated with the corresponding one of the segments from the first plurality of counters and to implement a cache segment replacement policy for determining which of the plurality of segments to replace as a function of at least the information relating to the number of active cache lines associated with the corresponding one of the segments.
地址 San Jose CA US
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