| 摘要 |
A DLL circuit comprises: a variable frequency division circuit that uses a variable frequency division ratio to frequency-divide a first clock signal, thereby generating first and second frequency-divided clock signals; a grain size change circuit that changes the count width in synchronization with the first frequency-divided clock signal; a counter circuit that updates the count value in accordance with the count width in synchronization with the second frequency-divided clock signal; and a variable delay circuit that delays the first clock signal on the basis of a delay amount that is in accordance with the count value, thereby generating a second clock signal. If the relationship in magnitude between the phase difference between the first and second clock signals and a predetermined value becomes inverse just after the updating of the count value, the grain size change circuit changes the count width, and the variable frequency division circuit sets the frequency division ratio of the second frequency-divided clock signal being greater than that of the first frequency-divided clock signal. In the DLL circuit in which the change width of the delay amount can be adjusted, a lock state is established in a short time. |
