FOUR CAPACITOR NONVOLATILE BIT CELL

摘要

A system on chip (SoC) provides a memory array of nonvolatile bit cells. Each bit cell includes two ferroelectric capacitors C1, C2 connected in series between a first plate line PL1 and a second plate line PL2, such that a node Q (404) is formed between the two ferroelectric capacitors. The first plate line and the second plate line are configured to provide a voltage approximately equal to a first voltage while the bit cell is not being accessed. A clamping circuit (406) is coupled to the node Q and is operable to clamp the node Q to a voltage approximately equal to the first voltage while the bit cell is not being accessed.