发明名称 DEBUG CONTROL CIRCUIT, DEBUG CONTROL METHOD AND PROGRAM
摘要 <p>PROBLEM TO BE SOLVED: To provide a debug control circuit, a debug control method and a program capable of determining the necessity of the reacquisition of an observation signal in a period in which data transfer to an external memory is impossible during debug processing.SOLUTION: A debug control circuit 101 includes: an access monitoring part 107 for monitoring the competition of access to an external memory 121 outside the debug control circuit; an untransferred data generation part 108 for, when it is determined that access to the external memory 121 competes by the access monitoring part 107, setting a period in which the access competes to a data transfer impossible period, and for generating untransferred data information for determining the necessity of the reacquisition of an observation signal Q4 in the data transfer impossible period; and a debug data transfer part 109 for transferring the observation signal in a data transfer permission period and the untransferred data information as write data Q15 in the data transfer impossible period to the external memory 121.</p>
申请公布号 JP2014142820(A) 申请公布日期 2014.08.07
申请号 JP20130011081 申请日期 2013.01.24
申请人 NEC CORP 发明人 KOJIMA TERUHISA
分类号 G06F11/34 主分类号 G06F11/34
代理机构 代理人
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