发明名称 INTEGRATED CIRCUIT TESTING WITH POWER COLLAPSED
摘要 Provided are apparatus and methods for testing an integrated circuit. In an exemplary method for testing an integrated circuit, a test controller and a power manager are integrated into a main power domain of the integrated circuit. The test controller can be Joint Test Action Group-compatible. An isolation signal is generated using the power manager. The isolation signal can comprise at least one of a freeze signal configured to isolate an input-output port of the integrated circuit, and a clamp signal configured to isolate a functional module of the integrated circuit. The isolation signal can be stored in a boundary scan register controlled with the test controller. The main power domain is isolated from a power-collapsible domain of the integrated circuit with the isolation signal. Power of the power-collapsible domain is collapsed. When power is collapsed, the power-collapsible domain is tested using the test controller and the power manager. The testing of the power-collapsible domain can comprise testing a power supply current. When power to the power-collapsible domain is collapsed, a level shifter output can be held constant to an output level based on a pre-collapse input from the power-collapsible domain.
申请公布号 US2014223250(A1) 申请公布日期 2014.08.07
申请号 US201414172292 申请日期 2014.02.04
申请人 QUALCOMM Incorporated 发明人 Chen Wei;Tao Yucong;Severson Matthew L.;Gemar Jeffrey R.;Yang Chang Yong
分类号 G01R31/3177 主分类号 G01R31/3177
代理机构 代理人
主权项 1. A method for testing an integrated circuit, comprising: integrating a test controller and a power manager into a main power domain of the integrated circuit; generating an isolation signal using the power manager; isolating the main power domain from a power-collapsible domain of the integrated circuit with the isolation signal; collapsing power of the power-collapsible domain; and testing the power-collapsible domain, when power is collapsed, using the test controller and the power manager.
地址 San Diego CA US