| 发明名称 |
SCAN-BASED TEST ARCHITECTURE FOR INTERCONNECTS IN STACKED DESIGNS |
| 摘要 |
Aspects of the invention relate to scan-based test architecture for interconnects in stacked designs. The disclosed scan-based test architecture comprises a scan chain. Scan cells on the scan chain are configured to receive data from, based on bits of a control signal, outputs of neighboring scan cells or outputs of mixing devices that combine data from through-silicon vias with data from the outputs of the neighboring scan cells. The scan-based test architecture can be used to identify single or multiple defective through-silicon vias. |
| 申请公布号 |
US2014223247(A1) |
申请公布日期 |
2014.08.07 |
| 申请号 |
US201414170804 |
申请日期 |
2014.02.03 |
| 申请人 |
Mentor Graphics Corporation |
发明人 |
Rajski Janusz;Tyszer Jerzy |
| 分类号 |
G01R31/3177 |
主分类号 |
G01R31/3177 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An integrated circuit, comprising:
a scan chain, scan cells on the scan chain configured to receive data from, based on bits of a control signal, outputs of neighboring scan cells or outputs of mixing devices that combine data from through-silicon vias with data from the outputs of the neighboring scan cells. |
| 地址 |
Wilsonville OR US |
