发明名称 |
EQUALIZER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME |
摘要 |
Provided are an equalizer and a semiconductor memory device including the same. The equalizer includes a delay circuit and an inverting circuit. The delay circuit is configured to output, in response to a select signal, one of a delay signal delaying an input signal applied to an input/output node and an inverted signal inverting the input signal. The inverting circuit is configured to invert a signal provided from the delay circuit and output the inverted signal to the input/output node. The equalizer is configured such that when the delay circuit outputs the delay signal, the equalizer operates as an inductive bias circuit amplifying the input signal and outputting the amplified input signal, and when the delay circuit outputs the inverted signal, the equalizer operates as a latch circuit storing and outputting the input signal. |
申请公布号 |
US2014219036(A1) |
申请公布日期 |
2014.08.07 |
申请号 |
US201414165990 |
申请日期 |
2014.01.28 |
申请人 |
Samsung Electronics Co., Ltd. |
发明人 |
KIM Dae-Hyun;BAE Seung-Jun;HA Kyung-Soo |
分类号 |
G11C7/12;H03K19/094;G11C7/22 |
主分类号 |
G11C7/12 |
代理机构 |
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代理人 |
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主权项 |
1. An equalizer comprising:
a delay circuit configured to output, in response to a select signal, one of a delay signal delaying an input signal applied to an input/output node and an inverted signal inverting the input signal; and an inverting circuit coupled to the delay circuit and configured to invert a signal provided from the delay circuit and output the inverted signal to the input/output node, wherein the equalizer is configured such that when the delay circuit outputs the delay signal, the equalizer operates as an inductive bias circuit amplifying the input signal and outputting the amplified input signal, and when the delay circuit outputs the inverted signal, the equalizer operates as a latch circuit storing and outputting the input signal. |
地址 |
Suwon-si KR |