发明名称 |
MASKING POWER USAGE OF CO-PROCESSORS ON FIELD-PROGRAMMABLE GATE ARRAYS |
摘要 |
Technologies are generally described for masking power usage of co-processors on field- programmable gate arrays. In some examples, one or more moat brick circuits may be implemented around a co-processor loaded on a field-programmable gate array (FPGA). The moat brick circuits may be configured to use negative feedback and/or noise to mask the power usage variations of the co-processor from other co-processors on the FPGA. |
申请公布号 |
WO2014120209(A1) |
申请公布日期 |
2014.08.07 |
申请号 |
WO2013US24162 |
申请日期 |
2013.01.31 |
申请人 |
EMPIRE TECHNOLOGY DEVELOPMENT, LLC |
发明人 |
FINE, KEVIN;KRUGLICK, EZEKIEL |
分类号 |
G06F15/00 |
主分类号 |
G06F15/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|