| 发明名称 |
Defect Determination in Integrated Circuit Manufacturing Process |
| 摘要 |
A method includes inspecting a wafer to find a first potential defect having a first wafer coordinate, and capturing a patch image of the first potential defect from the wafer. The patch image is compared with patterns of a wafer representation to find a first layout coordinate of a location in the wafer representation, wherein the location in the wafer representation corresponds to a location of the first potential defect in the wafer. A reference feature in the wafer representation is selected, wherein the reference feature in the wafer representation has a second layout coordinate. A coordinate difference between the first layout coordinate and the second layout coordinate is calculated. The coordinate difference is subtracted from the first wafer coordinate to calculate a second wafer coordinate of a reference feature in the wafer, wherein the reference feature in the wafer representation corresponds to the reference feature in the wafer. |
| 申请公布号 |
US2014219543(A1) |
申请公布日期 |
2014.08.07 |
| 申请号 |
US201313757592 |
申请日期 |
2013.02.01 |
| 申请人 |
COMPANY, LTD. TAIWAN SEMICONDUCTOR MANUFACTURING |
发明人 |
Kuo Min-Sung;Su Chiun-Chieh;Chen To-Yu |
| 分类号 |
G06T7/00 |
主分类号 |
G06T7/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method comprising:
inspecting a wafer to find a first potential defect, wherein the first potential defect has a first wafer coordinate; capturing a patch image of the first potential defect from the wafer; comparing the patch image with patterns of a wafer representation to find a first layout coordinate of a location in the wafer representation, wherein the location in the wafer representation corresponds to a location of the first potential defect in the wafer, and wherein the wafer representation has a layout of the wafer; selecting a reference feature in the wafer representation, wherein the reference feature in the wafer representation has a second layout coordinate; calculating a coordinate difference between the first layout coordinate and the second layout coordinate; and subtracting the coordinate difference from the first wafer coordinate to calculate a second wafer coordinate of a reference feature in the wafer, wherein the reference feature in the wafer representation corresponds to the reference feature in the wafer. |
| 地址 |
US |
