| 摘要 |
A write assist driver circuit is provided that assists a memory cell (e.g., volatile memory bit cell) in write operations to keep the voltage at the memory core sufficiently high for correct write operations, even when the supply voltage is lowered. The write assist driver circuit may be configured to provide a memory supply voltage VddM to a bit cell core during a standby mode of operation. In a write mode of operation, the write assist driver circuit may provide a lowered memory supply voltage VddMlower to the bit cell core as well as to at least one of the local write bitline (lwbl) and local write bitline bar (lwblb). Additionally, the write assist driver circuit may also provide a periphery supply voltage VddP to a local write wordline (lwwl), where VddP≧VddM>VddMlower. |
| 主权项 |
1. A memory circuit, comprising:
a memory bit cell circuit including a bit cell core, a local write bitline (lwbl), a local write bitline bar (lwblb), and a local write wordline (lwwl); a write assist driver circuit coupled to the memory bit cell circuit, the write assist driver circuit configured to:
provide, in a standby mode of operation, a memory supply voltage VddM to the bit cell core, andprovide, in a write mode of operation, a lowered memory supply voltage VddMlower to the bit cell core and a selected one of the local write bitline (lwbl) or local write bitline bar (lwblb), wherein VddM is greater than VddMlower. |
