LOW VOLTAGE BOOTSTRAPPING METHOD FOR WRITE ASSIST

摘要

Embodiments of a memory are disclosed that may allow for a negative boost of data lines during a write. The memory device may include a data input circuit, an address decode circuit and a plurality of sub-arrays. Each of the sub-arrays may include a plurality of columns, a write selection circuit, a first write driver circuit, a second write driver circuit, and a boost circuit. Each of the columns may include a plurality of data storage cells. The write selection circuit may select a column of the plurality of columns. Each of the write driver circuits may configured to discharge a data line of a selected column into a common node. The boost circuit may be configured to initialize the common node to the first voltage level and couple the common node to a second voltage level, where the second voltage level is lower than the first voltage level.

主权项

1. An apparatus, comprising:
a write driver circuit configured to:
initialize an output node to a first voltage level; anddischarge the output node to a second voltage level responsive to a first control signal;wherein the second voltage level is lower than the first voltage level; and a boost circuit coupled to the output node, wherein the boost circuit is configured to couple the output node to a third voltage level responsive to a second control signal, wherein the third voltage level is lower than the second voltage level.