| 摘要 |
<p>PROBLEM TO BE SOLVED: To solve a problem in that since FF for latency adjustment in a conventional high-level synthesizing device is inserted between modules, which is not optimal as a whole from a view point of a circuit scale.SOLUTION: Latency adjustment means calculates required delay from the number of FFs needed to be inserted between modules from the high-level synthesis of operation description. A pin the input of which is to be FF-received is extracted from HDL high-level synthesized or a synthesized log by an input FF number acquisition means. Latency readjustment means obtains the optimum delay from the required delay and input delay. From the synthesized log or HDL, pre-step module analyzing means detects each state in a module to be subjected to FF insertion, which has a pin, and the state in which the number of FFs held in the respective states is minimal. On the basis of an FF insertion place obtained from the optimal delay and the minimal state of the number of FFs, FF insertion optimally synthesizing means obtains the HDL optimized by high-level synthesizing all again.</p> |
