发明名称 TECHNIQUES FOR ENHANCING FRACTURE RESISTANCE OF INTERCONNECTS
摘要 Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via density. Increased via density can be provided, for example, within the filler/dummified portion(s) of adjacent circuit layers within a die. In some cases, an electrically isolated (floating) filler line of an upper circuit layer may include a via which lands on a floating filler line of a lower circuit layer in a region corresponding to where the filler lines cross/intersect. In some such cases, the floating filler line of the upper circuit layer may be formed as a dual-damascene structure including such a via. In some embodiments, a via similarly may be provided between a floating filler line of the upper circuit layer and a sufficiently electrically isolated interconnect line of the lower circuit layer. The techniques/structure can be used to provide mechanical integrity for the die.
申请公布号 WO2014120459(A1) 申请公布日期 2014.08.07
申请号 WO2014US11858 申请日期 2014.01.16
申请人 INTEL CORPORATION;JEZEWSKI, CHRISTOPHER J.;KOBRINSKY, MAURO J.;PANTUSO, DANIEL;BHINGARDE, SIDDHARTH B.;O'DAY, MICHAEL P. 发明人 JEZEWSKI, CHRISTOPHER J.;KOBRINSKY, MAURO J.;PANTUSO, DANIEL;BHINGARDE, SIDDHARTH B.;O'DAY, MICHAEL P.
分类号 H01L21/28 主分类号 H01L21/28
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