发明名称 SEPARATE MICROCHANNEL VOLTAGE DOMAINS IN STACKED MEMORY ARCHITECTURE
摘要 Separate microchannel voltage domains in a stacked memory architecture An embodiment of a memory device includes a memory stack including one or more coupled memory dies, wherein a first memory die of the memory stack includes multiple microchannels, and a logic chip coupled with the memory stack, the logic chip including a memory controller. Each of the microchannels includes a separate voltage domain, and a voltage level is controlled for each of the plurality of microchannels.
申请公布号 KR20140097520(A) 申请公布日期 2014.08.06
申请号 KR20147017941 申请日期 2011.12.23
申请人 INTEL CORP. 发明人 SCHAEFER ANDRE;SARASWAT RUCHIR
分类号 G11C5/02;G11C11/4074;H01L23/48 主分类号 G11C5/02
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