发明名称 DMA ARCHITECTURE FOR NAND-TYPE FLASH MEMORY
摘要 A device includes a nonvolatile memory array, a static random access memory (SRAM) array including a plurality of bit lines having first and second bit lines paired with each other, and a pad. A first circuit is coupled between the nonvolatile memory array and the first and second bit lines, and interfaces with the SRAM array. A second circuit is coupled between the pad and the first and second bit lines, and interfaces with the SRAM array. A control circuit performs a first operation to access the nonvolatile memory array via the SRAM array and the first and second circuits and performs a second operation by producing an electrical path connecting the pad to the nonvolatile memory array through at least one of the first and second bit lines of the SRAM array without intervening at least one of the first and second circuits.
申请公布号 KR20140097061(A) 申请公布日期 2014.08.06
申请号 KR20140079102 申请日期 2014.06.26
申请人 PS4 LUXCO S.A.R.L. 发明人 PAGLIATO MARUO;MARTINOZZI GIULIO;PESSINA FRANCESCO
分类号 G11C29/00;G11C16/06 主分类号 G11C29/00
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