Low-power area-efficient SAR ADC using dual capacitor arrays

摘要

An analog to digital converter that comprises a successive approximation register (SAR) having an n bit binary output, a first capacitor array connected to receive some of the bits of the binary output, a second capacitor array connected to receive the remaining bits of the binary output, and a comparator including an output connected to the SAR. The first and second capacitor arrays each have an analog output indicative of the charge stored by capacitors of that array. The comparator includes a pair of inputs, one of which is connected to the analog output of the first capacitor array and the other of which is connected to the analog output of the second capacitor array.

主权项

1. An analog to digital converter, comprising:
a successive approximation register (SAR) having an n-bit binary output; a first capacitor array connected to receive some of the bits of the binary output; a second capacitor array connected to receive the remaining bits of the binary output, wherein the first and second capacitor arrays each have an analog output indicative of the charge stored by capacitors of that array, the first capacitor array uses a first reference voltage level, and the second capacitor array uses a second reference voltage equal to the first reference voltage divided by 2n/2; and a comparator including an output connected to the SAR and including a pair of inputs, one of which is connected to the analog output of the first capacitor array and the other of which is connected to the analog output of the second capacitor array; wherein the analog to digital converter includes an analog voltage input that receives an inputted analog voltage to be converted to digital form, and wherein the first capacitor array includes a switch that interconnects the analog voltage input to the capacitors of the first capacitor array such that, when connected to the analog voltage input by the switch, the first capacitor array samples the inputted analog voltage.