Package substrate having main dummy pattern located in path of stress

摘要

A package substrate includes an insulating substrate, a functional pattern and a main dummy pattern. A semiconductor chip is arranged on the insulating substrate. The functional pattern is formed on the insulating substrate. The functional pattern is electrically connected to the semiconductor chip. The main dummy pattern is formed on a portion of the insulating substrate at least of to the outside of and/or adjacent the functional pattern in a path of stress generated by a difference between thermal expansion coefficient of the insulating substrate and the semiconductor chip, so as to divert the stress away from the functional pattern. Thus, the stress is not concentrated on the functional pattern. As a result, damage to the functional bump caused by the stress is prevented.

主权项

1. A package substrate comprising:
an insulating substrate on which a semiconductor chip is arranged; a functional pattern formed on the insulating substrate, wherein the functional pattern is electrically connected to the semiconductor chip; and a main dummy pattern formed on a portion of the insulating substrate at least one of to an outside of or adjacent the functional pattern, wherein the main dummy pattern is oriented in a path of stress on the insulating substrate generated by a difference between thermal expansion coefficients of the insulating substrate and the semiconductor chip, and an auxiliary dummy pattern adjacent to the functional pattern, the auxiliary dummy pattern and the main dummy pattern surrounding the functional pattern.