发明名称 |
Four capacitor nonvolatile bit cell |
摘要 |
A system on chip (SoC) provides a memory array of nonvolatile bitcells. Each bit cell includes two ferroelectric capacitors connected in series between a first plate line and a second plate line, such that a node Q is formed between the two ferroelectric capacitors. The first plate line and the second plate line are configured to provide a voltage approximately equal to first voltage while the bit cell is not being accessed. A clamping circuit is coupled to the node Q and is operable to clamp the node Q to a voltage approximately equal to first voltage while the bit cell is not being accessed. |
申请公布号 |
US8797783(B1) |
申请公布日期 |
2014.08.05 |
申请号 |
US201313753782 |
申请日期 |
2013.01.30 |
申请人 |
Texas Instruments Incorporated |
发明人 |
Bartling Steven Craig;Khanna Sudhanshu |
分类号 |
G11C11/00;G11C11/22 |
主分类号 |
G11C11/00 |
代理机构 |
|
代理人 |
Pessetto John R.;Telecky, Jr. Frederick J. |
主权项 |
1. A system on chip (SoC) comprising a plurality of non-volatile bit cells, wherein each bit cell comprises:
two ferroelectric capacitors connected in series between a first plate line and a second plate line, such that a node Q is formed between the two ferroelectric capacitors, wherein the first plate line and the second plate line are configured to provide a voltage approximately equal to first voltage while the bit cell is not being accessed; a first clamping circuit coupled to the node Q, wherein the first clamping circuit is operable to clamp the node Q to a voltage approximately equal to first voltage while the bit cell is not being accessed; further comprising a transmission gate coupled between the node Q and the bitline, the transmission gate configured to isolate node Q from the bitline in response to a control signal, wherein the transmission gate comprises an NMOS device connected in parallel with a PMOS device. |
地址 |
Dallas TX US |