3D integrated circuit structure and method for manufacturing the same

摘要

A 3D integrated circuit structure comprises a first chip, wherein the first chip comprises: a substrate; a semiconductor device formed on the substrate and a dielectric layer formed on both the substrate and the semiconductor device; a conductive material layer formed within a through hole penetrating through both the substrate and the dielectric layer; a stress releasing layer surrounding the through hole; and a first interconnecting structure connecting the conductive material layer with the semiconductor device. By forming a stress releasing layer to partially release the stress caused by the conductive material in the via, the stress caused by mismatch of CTE between the conductive material and the semiconductor (for example, silicon) surrounding it can be reduced, thereby enhancing the performance of the semiconductor device and the corresponding 3D integrated circuit consisting of the semiconductor devices.

主权项

1. A 3D integrated circuit structure comprising a first chip, wherein the first chip comprises:
a first substrate; a first semiconductor device formed on the first substrate and a first dielectric layer formed on both the first substrate and the first semiconductor device; a through hole, a stress passage isolation layer and a stress releasing layer which penetrate both the first substrate and the first dielectric layer, wherein the stress passage isolation layer surrounds the outside of the through hole and the stress releasing layer surrounds the outside of the stress passage isolation layer; an insulating layer formed on inside walls of the stress passage isolation layer; a conductive material layer formed within free space of the through hole, wherein the conductive material layer comprises an internal conductive via and an external stop layer; and a first interconnecting structure connecting the conductive material layer with the first semiconductor device.