On time sampling prevention

摘要

An example controller for a power converter includes a feedback sampling circuit, drive logic and a false sampling prevention circuit. The feedback sampling circuit is coupled to sample a feedback signal received from a terminal of the controller and to generate a sample signal representative of a value of the feedback signal. The drive logic is coupled to the feedback sampling circuit and coupled to control the power switch to regulate an output of the power converter in response to the sample signal. The false sampling prevention circuit is coupled to receive a sampling complete signal that indicates when the sampling of the feedback signal is complete. The false sampling prevention circuit is further coupled to the drive logic to extend the off time of the power switch until the sampling complete signal indicates that the sampling of the feedback signal by the feedback sampling circuit is complete.

主权项

1. An integrated circuit controller for a power converter, the controller comprising:
a feedback sampling circuit coupled to sample a feedback signal received from a terminal of the controller and to generate a sample signal representative of a value of the feedback signal, wherein the feedback signal represents an output voltage of the power converter during at least a portion of an off time of a power switch; drive logic coupled to the feedback sampling circuit and coupled to control the power switch to regulate an output of the power converter in response to the sample signal; a false sampling prevention circuit coupled to receive a sampling complete signal, wherein the false sampling prevention circuit is further coupled to the drive logic to extend the off time of the power switch until the sampling complete signal indicates that the sampling of the feedback signal by the feedback sampling circuit is complete; and an oscillator coupled to generate an on-time signal having a switching period, wherein the false sampling prevention circuit is included in the oscillator to extend the switching period in response to the sampling complete signal, and wherein the drive logic is coupled to turn on the power switch in response to the on-time signal.