Semiconductor device having DLL circuit and control method thereof

摘要

Disclosed herein is a device that comprises a delay line delaying a first clock signal in response to the delay control information to produce a delayed clock signal, a phase detector unit controls the delay control information in response to a relationship in phase between the first clock signal and a second clock signal, and an inverting control unit receiving the delayed clock signal and producing a third clock signal, the second clock signal being produced in response to the third clock signal. The third clock signal is in phase with the delayed clock signal when the inverting control unit is in a first state and complementary to the delayed clock signal when the inverting control unit is in a second state.

主权项

1. A device comprising:
a delay line unit supplied with delay control information, the delay line configured to delay a first clock signal in response to the delay control information to produce a delayed clock signal; a phase detector unit supplied with the first clock signal and a second clock signal and configured to control the delay control information in response to a relationship in phase between the first and second clock signals; and a circuit unit coupled between the delay line unit and the phase detector unit, the circuit unit including an inverting control unit configured to receive the delayed clock signal and to produce a third clock signal, the third clock signal being in phase with the delayed clock signal when the inverting control unit is in a first state and complementary to the delayed clock signal when the inverting control unit is in a second state, the circuit unit being configured to produce the second clock signal as a replica signal in response to the third clock signal.