Display driving circuit, device and method for polarity inversion using retention capacitor lines

摘要

In a display device (i) which carries out a display based on a video signal whose resolution has been converted to higher resolution (high-resolution conversion driving) and (ii) which carries out CC driving, when the resolution of the video signal is converted by a factor of 2 (double-size display), assuming that a direction in which the gate lines extend is a row-wise direction, signal potentials having the same polarity and the same gray scale are supplied to pixel electrodes included in respective two pixels that correspond to two adjacent gate lines and that are adjacent to each other in the column-wise direction (scanning direction), and a direction of change in the signal potentials written to the pixel electrodes from the source lines varies every two adjacent rows according to the polarities of the signal potentials.

主权项

1. A display driving circuit for use in a display device (i) which carries out a display based on a video signal whose resolution has been converted to higher resolution and (ii) in which by supplying retention capacitor wire signals to retention capacitor wires forming capacitors with pixel electrodes included in pixels, signal potentials written to the pixel electrodes from data signal lines are changed in a direction corresponding to polarities of the signal potentials, the display driving circuit comprising:
a shift register including a plurality of stages provided in such a way as to correspond to a plurality of scanning signal lines, respectively; and retaining circuits provided in such a way as to correspond one-by-one to the respective stages of the shift register, one of a first retention target signal and a second retention target signal being inputted to each of the retaining circuits, each of the retaining circuits retaining a corresponding one of the first and second retention target signals at a time when an output signal from one of the plurality of stages in the shift register becomes active and at a time when an output signal from another one of the plurality of stages in the shift register becomes active, wherein an output signal from a current one of the plurality of stages and an output signal from a subsequent one of the plurality of stages that is later than the current stage are inputted to a logic circuit corresponding to the current stage, when an output from the logic circuit becomes active, one of the retaining circuits corresponding to the current stage loads and retains the corresponding one of the first and second retention target signals, each of the first and second retention target signals is a signal which reverses its polarity at a timing, and (i) a polarity of the first retention target signal at a point in time where the output signal which is outputted from the current stage and inputted to the logic circuit becomes active and (ii) a polarity of the second retention target signal at a point in time where the output signal which is outputted from the subsequent stage and inputted to the logic circuit becomes active are different from each other, the output signal from the current stage is supplied to one of the plurality of scanning signal lines connected to pixels corresponding to the current stage, and an output from the one of the retaining circuits is supplied as the retention capacitor wire signal to a retention capacitor wire that forms capacitors with pixel electrodes of the pixels corresponding to the current stage, the first retention target signal that is inputted to a plurality of retaining circuits and the second retention target signal that is inputted to another plurality of retaining circuits are different in phase from each other, assuming that a direction in which the plurality of scanning signal lines extend is a row-wise direction, when the resolution of the video signal is converted by a factor of n (n is an integer of two or greater) at least in a column-wise direction, signal potentials having the same polarity and the same gray scale are supplied to pixel electrodes included in respective n pixels that correspond to n adjacent ones of the plurality of scanning signal lines and that are adjacent to each other in the column-wise direction, and a direction of change in the signal potentials written to the pixel electrodes from the data signal lines varies every n adjacent rows according to the polarities of the signal potentials.